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triple differential driver for wideband video ad8146/ad8147/ad8148 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2010 analog devices, inc. all rights reserved. features triple high speed fully differential driver 700 mhz, ?3 db, 2 v p-p bandwidth (ad8146/ad8148) 600 mhz, ?3 db, 2 v p-p bandwidth (ad8147) 200 mhz, 0.1 db, 2 v p-p bandwidth 3000 v/s slew rate fixed gain (ad8146/ad8147: g = 2, ad8148: g = 4) differential or single-ended input to differential output can be used as differential-to-differential receiver drives one or two 100 utp cables adjustable output common-mode voltage (ad8146) internal common-mode feedback network output balance error ?50 db @ 50 mhz on-chip, sync-on common-mode encoding (ad8147/ad8148) output pull-down feature for line isolation low power: 57 ma @ 5 v for 3 drivers (ad8146) wide supply voltage range: +5 v to 5 v available in a small 4 mm 4 mm lfcsp applications qxga or 1080p video transmission kvm networking video over unshielded twisted pair (utp) differential signal multiplexing functional block diagrams ad8146 opd 1 v s? 2 ?in a 3 +in a 4 v s? 5 v ocm c v s+ ?in c +in c v s? 18 17 16 15 14 ?out a 6 ?out c 13 v s+ ?in b +in b v s? v ocm a 24 23 22 21 20 v ocm b 19 +out a v s+ +out b ?out b v s+ 7 8 9 10 11 +out c 12 a b c 09327-001 figure 1. ad8147/ ad8148 opd 1 v s? 2 ?in r 3 +in r 4 v s? 5 sync level v s+ (sync) ?in b +in b v s? 18 17 16 15 14 ? out r 6 ?out b 13 v s+ ?in g +in g v s? (sync) v sync 24 23 22 21 20 h sync 19 +out r v s+ +out g ?out g v s+ 7 8 9 10 11 +out b 12 a b c 2 09327-002 figure 2. general description the ad8146/ad8147/ad8148 are high speed triple, differential or single-ended input to differential output drivers. the ad8146 and ad8147 have a fixed gain of 2, and the ad8148 has a fixed gain of 4. they are all specifically designed for the highest resolution component video signals but can be used for any type of analog signals or high speed data transmission over either category 5 utp cable or differential printed circuit board (pcb) transmission lines. these drivers can be used with the ad8145 triple differential- to-singled-ended receiver, and the ad8117 crosspoint switch to produce a video distribution system capable of supporting uxga or 1080p signals. manufactured on the analog devices, inc. second generation xfcb bipolar process, the drivers have large signal bandwidths of 700 mhz and fast slew rates. they have an internal common- mode feedback feature that provides output amplitude and phase matching that is balanced to ?60 db at 50 mhz, suppressing even-order harmonics and minimizing radiated electromagnetic interference (emi). the common-mode voltage of each ad8146 output can be set to any level, allowing transmission of signals over the common- mode voltages. the ad8147 and ad8148 encode the vertical and horizontal sync signals on the common-mode voltages of the outputs. all outputs can be independently set to low voltage states to be used with series diodes for line isolation, allowing easy differential multiplexing over the same twisted pair cable. the ad8146/ad8147/ad8148 are available in a 24-lead lfcsp and operate over a temperature range of ?40c to +85c.
ad8146/ad8147/ad8148 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functio nal block diagrams ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 sp ecifications ..................................................................................... 3 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 e sd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 14 definition of terms .................................................................... 14 analyzing an application circuit ............................................. 14 closed - loop gain ...................................................................... 14 calculating the input impedance ............................................. 15 input common - mo de vo ltage range in single - supply applications ................................................................................ 15 output common - mode control ............................................. 15 sync - on common - mode ......................................................... 15 applications ..................................................................................... 16 driving rgb video signals over category - 5 utp cable .... 16 video sync - on common - mo de .............................................. 16 driving two utp cables with one driver ........................... 18 using the ad8146 as a receiver ............................................... 18 output pull - down (opd) ........................................................ 19 layout and power supply decoupling considerations ......... 19 driving a capacitive load ......................................................... 19 adding pre - emphasis to the ad8148 ..................................... 20 exposed paddle (ep) .................................................................. 21 outlin e dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 8 /10 rev. 0 to rev. a changes to table 1 ................................ ............................................ 3 changes to table 2 ............................................................................ 5 changes to pin configuration s and function descriptions section ................................................................................................ 8 changes to adding pre - emphasis to the ad8148 section ....... 20 updated outline dimensions ....................................................... 22 5 /07 revision 0: initial version
ad8146/ad8147/ad8148 rev. a | page 3 of 24 specifications v s = 5v, v ocm = 0 v (ad8146) ; sync level = 0 v (ad8147/ad8148) ; t = 25c ; r l , dm = 200 ?, unless otherwise noted. t min to t max = ?40c to +85c. table 1 . parameter conditions min typ max unit differential input ac dynamic performance ?3 db small signal bandwidth v o = 0.2 v p -p, ad8146/ad814 8 900 mhz ad8147 780 mhz ?3 db large signal bandwidth v o = 2 v p -p, ad8146/ad8148 700 mhz ad8147 600 mhz bandwidth for 0.1 db flatness v o = 2 v p - p, ad8146/ad8147 200 mhz ad8148 235 mhz slew rate v o = 2 v p - p, 25% to 75% 3000 v/s isolation between amplifiers f = 10 mhz ad8146/ad8147 ?86 db ad8148 ?80 db differential input dc input common - mode voltage range ?5 to +5 v input resistance differential 1.0 k? single - ended input ad8146/ad8147 750 ? ad8148 833 ? input capacitance differential 2 pf dc cmrr v out, dm / v in, cm , v in, cm = 1 v ad8146/ad8147/ad8148 ? 53/ ?49/?55 db differential output differential signal gain v out, dm /v in, dm ; v in, dm = 1 v ad8146/ad8147 1.94 2.00 v/v v out, dm /v in, dm ; v in, dm = 1 v ad8148 3.8 4.0 v/v output voltage swing each single - ended output ad8146/ad8147/ad8148 ?3/?2.25/?3.42 +3.4/+3.4/+3.5 v output offset voltage ? 19 +19 mv output offset drift t min to t max 8 v/c output balance error v out, cm / v in, dm , v out, dm = 2 v p -p f = 50 mhz ad8146/ad8147 ? 52 db ad8148 ? 49 db dc ad8146/ad8148 ? 41 db ad8147 ?44 db output voltage noise (rto) f = 1 mhz ad8146/ad8147 25 nv/ hz ad8148 42 nv/ hz output short - circuit current short to gnd, source/sink +87 / ?67 ma
ad8146/ad8147/ad8148 rev. a | page 4 of 24 parameter conditions min typ max unit v ocm dynamic performance (ad8146 only) ?3 db bandwidth v ocm = 100 mv p-p 340 mhz slew rate v ocm = ?1 v to +1 v, 25% to 75% 800 v/s dc gain v ocm = 1 v 0.98 1.00 v/v v ocm input characteristics (ad8146 only) input voltage range 3 v input resistance 12.5 k input offset voltage ?36 +36 mv dc cmrr v out, dm /v ocm , v ocm = 1 v ?48 db sync dynamic performance (ad8147/ ad8148 only) slew rate v out, cm = ?1 v to +1 v; 25% to 75% 1000 v/s h sync and v sync inputs (ad8147/ad8148 only) low-to-high threshold 1.5 to1.7 v high-to-low threshold 1.5 to1.7 v sync level input (ad8147/ad8148 only) setting to 0.5 v pulse levels 0.5 v gain to red common-mode output v o, cm /v sync level , ad8147/ad8148 0.93/0.96 1.10/1.05 v/v gain to green common-mode output v o, cm /v sync level , ad8147/ad8148 1.91/1.93 2.15/2.08 v/v gain to blue common-mode output v o, cm /v sync level , ad8147/ad8148 ?1.10/?1.05 ?0.93/?0.96 v/v power supply operating range +4.5 5.5 v quiescent current, positive supply ad8146/ad8147/ad8148 58/61.5/62.5 ma disabled ad8146 6 ma ad8147/ad8148 21.5 ma quiescent current, negative supply ad8146/ad8147/ad8148 ?58/?60.5/?62 ma disabled ?37 ma psrr v out, dm /v s ; v s = 1 v ad8146/ad8147/ad8148 ?66/?52/?55 db output pull-down opd input low voltage 1.1 v opd input high voltage 2.1 v opd input bias current 520 a opd assert time 1 s opd deassert time 10 ns output voltage when opd asserted each output, opd input @ v s + ?3.8 v
ad8146/ad8147/ad8148 rev. a | page 5 of 24 v s = +5 v or 2.5 v; v ocm = midsupply (ad8146); sync level = 0 v (ad8147/ad8148); t = 25c; r l, dm = 200 , unless otherwise noted. t min to t max = ?40c to +85c. table 2. parameter conditions min typ max unit differential input ac dynamic performance ?3 db small signal bandwidth v o = 0.2 v p-p, ad8146 870 mhz ad8147/ad8148 680 mhz ?3 db large signal bandwidth v o = 2 v p-p, ad8147 590 mhz ad8146/ad8148 620 mhz bandwidth for 0.1 db flatness v o = 2 v p-p, ad8146/ad8147 165 mhz ad8148 200 mhz differential input dc input common-mode voltage range 0 to 5 v input resistance differential 1.0 k single-ended input ad8146/ad8147 750 ad8148 833 input capacitance differential 2 pf dc cmrr v out, dm /v in, cm ; v in, cm = 1 v, ad8146/ad8147/ad8148 ?49/?45/?49 db differential output differential signal gain v out, dm /v in, dm ; v in, dm = 1 v, ad8146/ad8147 1.94 2.00 v/v v out, dm /v in, dm ; v in, dm = 1 v ad8148 3.80 4.00 v/v output voltage swing each single-ended output, v s = 2.5 v ?1.17 +1.24 v output offset voltage ?17 +17 mv output offset drift t min to t max 8 v/c output balance error v out, cm /v in, dm , v out, dm = 2 v p-p, f = 50 mhz ?53 db ad8146/ad8147 ?49 db ad8148 dc ad8146/ad8148 ?41 db ad8147 ?44 db output voltage noise (rto) f = 1 mhz ad8146/ad8147 25 nv/hz ad8148 42 nv/hz output short-circuit current short to gnd, source/sink +63/?48 ma v ocm dynamic performance (ad8146 only) ?3 db bandwidth v ocm = 100 mv p-p 310 mhz slew rate v ocm = ?1 v to +1 v, 25% to 75% 800 v/s dc gain v ocm = 1 v 0.98 1.00 v/v
ad8146/ad8147/ad8148 rev. a | page 6 of 24 parameter conditions min typ max unit v ocm input characteristics (ad8146 only) input voltage range 1.2 v input resistance 12.5 k input offset voltage ?36 +36 mv dc cmrr v o, dm /v ocm ; v ocm = 1 v ?42 db sync dynamic performance (ad8147/ ad8148 only) slew rate v out, cm = ?1 v to +1 v; 25% to 75% 800 v/s h sync and v sync inputs (ad8147/ad8148 only) low-to-high threshold 1.3 to 1.5 v high-to-low threshold 1.3 to 1.5 v sync level input (ad8147/ad8148 only) setting to 0.5 v pulse levels 0.5 v gain to red common-mode output v o, cm /v sync level , ad8147/ad8148 0.88/0.92 1.07/1.04 v/v gain to green common-mode output v o, cm /v sync level , ad8147/ad8148 1.83/1.85 2.08/2.00 v/v gain to blue common-mode output v o, cm /v sync level , ad8147/ad8148 ?1.07/?1.04 ?0.88/?0.92 v/v power supply operating range +4.5 5.5 v quiescent current positive supply ad8146/ad8147/ad8148 50/55.5/ 54 ma disable ad8146 4 ma ad8147/ad8148 12 ma quiescent current negative supply ad8146/ad8147/ad8148 ?50/?55/?53 ma disabled ad8146/ad8147/ ad8148 ?14/?18.2/?15 ma psrr v out, dm /v s ; v s = 1 v, ad8146/ad8147/ad8148 ?70/?52/-60 db output pull-down opd input low voltage 1.0 v opd input high voltage 2.0 v opd input bias current 160 a opd assert time 600 ns opd deassert time 10 ns output voltage when opd asserted each output, opd input @ v s + ?1.6 v
ad8146/ad8147/ad8148 rev. a | page 7 of 24 absolute maximum rat ings table 3 . parameter rating supply voltage 11 v all v ocm v s power dissipation see figure 3 input common - mode voltage v s storage temperatu re range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering , 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a str ess ra t ing only and functional operation of the device at these or any other conditions above those indicated in the operational se c tion of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may a f fect de vice reliability. thermal resistance ja is specified for the worst - case conditions, that is , ja is speci fied for the device soldered in a circuit board in still air. table 4 . thermal resistance with the underside pad connected to the plane package type/pcb type ja u nit 24- lead lfcsp/4 - layer 57 c/w maximum power dissipation the maximum safe power dissipation in the ad8146/ ad8147/ad8148 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass tra n sition temperature, the plastic changes its properties. even te m porarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric pe r formance of the ad8146/ad8147/ad8148 . exceeding a j unction te m perature of 175c for an extended time can result in changes in the silicon devices , potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the pac k age due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the load current consists of differential and co m mon - mode currents flowing to the loads, as well as currents flowing throu gh the internal differential and common - mode feedback loops. the internal resistor tap used in the common - mode feedback loop places a 4 k? differential load on the output. differential feedback, network resistor values are given in the theory of operation section and applications section. rms output voltages should be considered when dealing with ac si gnals. airflow reduces ja . in addition, more metal directly in contact w ith the package leads from metal traces, through holes, ground, and power planes reduces the ja . the exposed paddle on the underside of the package must be soldered to a pad on the pcb su r face that is thermally connected to a ground plane to achieve the s pec i fied ja . figure 3 shows the maximum safe power dissipation in the package vs . the ambient tempe rature for the 24 - lead lfcsp (57 c/w) package on a jedec standard 4 - layer board with the underside paddle soldered to a pad that is thermally connected to a ground plane. ja values are approxim a tions. 3.5 0 ?40 ?20 0 20 40 60 80 ambient temperature (c) maximum power dissipation (w) 3.0 2.5 2.0 1.5 1.0 0.5 09327-021 figure 3 . maximum power dissipation vs. temperature for a 4 - layer board esd caution
ad8146/ad8147/ad8148 rev. a | page 8 of 24 pin configuration s and function d escriptions pin 1 indicator 1opd 2v s? 3 ?in a 4 +in a 5v s? 6 ?out a notes 1. the exposed paddle on the underside of the chip must be connected to a ground plane. 15 +in c 16 ?in c 17 v s+ 18 v ocm c 14 v s? 13 ?out c 7 +out a 8v s+ 9 +out b 11 v s+ 12 +out c 10 ?out b 21 v s? 22 +in b 23 ?in b 24 v s+ 20 v ocm a 19 v ocm b ad8146 top view (not to scale) 09327-004 figure 4 . ad8146 pin configuration table 5 . ad8146 pin function descriptions pin no. mnemonic description 1 opd output pull - down . 2, 5, 14, 21 v s? negative power supply voltage . 3 ?in a inverting input, amplifier a . 4 +in a noninverting input, amplifier a . 6 ?out a negative output, amplifier a . 7 +out a positive output, amplifier a . 8, 11, 17, 24 v s+ positive power supply voltage . 9 +out b positive output, amplifier b . 10 ?out b negative output, amplifier b . 12 +out c positive output, amplifier c . 13 ?out c negative output, amplifier c . 15 +in c noninverting input, amplifier c . 16 ?in c inverting input, amplifier c . 18 v ocm c the v oltage applied to this pin controls output common - mode vol t age , am plifier c . 19 v ocm b the v oltage applied to this pin controls output common - mode vol t age , amplifier b . 20 v ocm a the v oltage applied to this pin controls output common - mode vol t age , amplifier a . 22 +in b noninverting input, amplifier b . 23 ?in b invertin g input, amplifier b . exposed pa d dle gnd signal ground reference.
ad8146/ad8147/ad8148 rev. a | page 9 of 24 pin 1 indicator 1opd 2v s? 3 ?in r 4 +in r 5v s? 6 ?out r 15 +in b 16 ?in b 17 v s+ (sync) 18 sync level 14 v s? 13 ?out b 7 +out r 8v s+ 9 +out g 11 v s+ 12 +out b 10 ?out g 21 v s? (sync) 22 +in g 23 ?in g 24 v s+ 20 v sync 19 h sync ad8147/ ad8148 top view (not to scale) 09327-005 notes 1. the exposed paddle on the underside of the chip must be connected to a ground plane. figure 5 . ad8147 /ad8148 pin configuration table 6 . ad8147/ad8148 pin function descriptions pin no. mnemonic description 1 opd outpu t pull - down. 2, 5, 14 v s ? negative power supply voltage. 3 ?in r inverting input, red amplifier. 4 +in r noninverting input, red amplifier. 6 ?out r negative output, red amplifier. 7 +out r positive output, red amplifier. 8, 11, 24 v s+ positive power supply voltage. 9 +out g positive output, green amplifier. 10 ?out g negative output, green amplifier. 12 +out b positive output, blue amplifier. 13 ?out b negative output, blue amplifier. 15 +in b noninverting input, blue amplifier. 16 ?in b inverting input, blue amplifie r. 17 v s+ (sync) positive power supply voltage for sync. 18 sync level the voltage applied to this pin controls the amplitude of the sync pulses that are applied to the common - mode voltages. 19 h sync horizontal sync pulse input. 20 v sync vertical sync pulse input. 21 v s? (sync) negative power supply voltage for sync. 22 +in g noninverting input, green amplifier. 23 ?in g inverting input, green amplifier. exposed pa d dle gnd signal ground reference .
ad8146/ad8147/ad8148 rev. a | page 10 of 24 typical performance characteristics v s = 5v ; v ocm = 0 v (ad8146) ; sy nc level = 0 v (ad8147/ad8148) ; t = 25c ; r l , dm = 200 ?; c l, dm = 0 pf , unless otherwise noted. t min to t max = ?40c to +85c . 9 ?1 10 1000 frequency (mhz) gain (db) 100 8 7 6 5 4 3 2 1 0 v out, dm = 2v p-p ad8146 (2.5v) ad8146 (5.0v) ad8147 (2.5v) ad8147 (5.0v) 09327-010 figure 6. ad8146/ad8147 large signal frequency r esponse for various supplies 9 ?1 10 1000 frequency (mhz) gain (db) 100 8 7 6 5 4 3 2 1 0 v out, dm = 0.2v p-p ad8146 (2.5v) ad8146 (5.0v) ad8147 (2.5v) ad8147 (5.0v) 09327-011 figure 7 . ad8146/ad8147 small signal frequency r esponse for various supplies 6.5 5.5 1 1000 frequency (mhz) gain (db) v out, dm = 2v p-p ad8146 (2.5v) ad8146 (5.0v) ad8147 (2.5v) ad8147 (5.0v) 10 100 6.4 6.3 6.2 6.1 6.0 5.9 5. 8 5.7 5.6 09327-012 figure 8. ad8146/ad8147 la rge signal 0.1 db flatness for various supplies 15 5 10 1000 frequency (mhz) gain (db) 100 14 13 12 11 10 9 8 7 6 v out, dm = 2v p-p 5.0v 2.5v 09327-013 figure 9. ad8148 large signal frequency r esponse for various supplies 15 5 10 1000 frequency (mhz) gain (db) 100 14 13 12 11 10 9 8 7 6 v out, dm = 0.2v p-p 2.5v 5.0v 09327-014 figure 10 . ad8148 small signal frequency r esponse for various supplies 12.5 1 1.5 1 1000 frequency (mhz) gain (db) 10 100 12.4 12.3 12.2 12.1 12.0 11.9 11.8 11.7 11.6 5.0v 2.5v v out, dm = 2v p-p 09327-015 figure 11 . ad8148 large signal 0.1 db flatness for various supplies
ad8146/ad8147/ad8148 rev. a | page 11 of 24 1.5 ?1.5 0 20 time (ns) voltage (v) 1.0 0.5 0 ?0.5 ?1.0 2 4 6 8 10 12 14 16 18 v s = 2.5v v s = 5.0v v out, dm = 2v p-p 09327-016 figure 12 . ad8146/ad8147 large signal transient r esponse for various supplies 150 ?150 0 20 time (ns) voltage (mv) 100 50 0 ?50 ?100 2 4 6 8 10 12 14 16 18 v out, dm = 0.2v p-p v s = 2.5v v s = 5.0v 09327-017 figure 13 . ad8146/ad8147 small signal transient r esponse for various supplies ?20 ?70 1 1000 frequency (mhz) output balance error (db) 10 100 ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 v out, cm /v out, dm v out, dm = 2v p-p ad8147 ad8148 ad8146 09327-024 figure 14 . output balance vs. freq uenc y 1.5 ?1.5 0 20 time (ns) voltage (v) 1.0 0.5 0 ?0.5 ?1.0 2 4 6 8 10 12 14 16 18 v out, dm = 2v p-p v s = 2.5v v s = 5.0v 09327-019 figure 15 . ad8148 large signal transient response for various supplies 150 ?150 0 20 time (ns) voltage (mv) 100 50 0 ?50 ?100 2 4 6 8 10 12 14 16 18 v out, dm = 0.2v p-p v s = 2.5v v s = 5.0v 09327-020 figure 16 . ad8148 small signal transient response for various supplies ?20 ?80 1 1000 frequency (mhz) common-mode rejection (db) 10 100 ?30 ?40 ?50 ?60 ?70 v out, dm /v in, cm v in, cm = 2v p-p ad8146 ad8148 ad8147 09327-027 figure 17 . cmrr vs . frequency
ad8146/ad8147/ad8148 rev. a | page 12 of 24 ?20 ?100 0.1 1000 frequency (mhz) power supply rejection (db) 1 10 100 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ad8146 ad8148 ad8147 v out, dm /v s+ v s = 2v p-p 09327-028 figure 18 . positive power supply rejection vs. frequency 1000 10 0.01 100000 frequency (khz) noise (nv/ hz) 0.1 1 10 100 1000 10000 100 ad8148 ad8146 ad8147 v s = 5v 09327-029 figure 19 . output - referred voltage noise vs. frequency 10 ?10 0 1000 time (ns) voltage (v) 8 6 4 2 0 ?2 ?4 ?6 ?8 100 200 300 400 500 600 700 800 900 input 2 (v s = 5.0v) output (v s = 5.0v) input 2 (v s = 2.5v) output (v s = 2.5v) 09327-030 figure 20 . ad8146/ad8147 output overdrive recover y ?20 ?1 10 0.1 1000 frequency (mhz) power supply rejection (db) 1 10 100 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 v out, dm /v s? v s = 2v p-p ad8146 ad8148 ad8147 09327-051 figure 21 . negative power supply rejection vs. frequenc y ?20 ?120 0.1 1000 frequency (mhz) isolation (db) 1 10 100 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ad8148 ad8146 ad8147 v out, dm b/v in, dm a v in, dm a = 1v p-p 09327-052 figure 22 . amplifier -to- amplifier isolation vs. frequency 10 ?10 0 1000 time (ns) voltage (v) 8 6 4 2 0 ?2 ?4 ?6 ?8 100 200 300 400 500 600 700 800 900 input 4 (v s = 5.0v) input 4 (v s = 2.5v) output (v s = 2.5v) output (v s = 5.0v) 09327-033 figure 23 . ad8148 output overdrive recover y
ad8146/ad8147/ad8148 rev. a | page 13 of 24 59 45 ?60 120 temperature (c) supply current (ma) 57 55 53 51 49 47 ?40 ?20 0 20 40 60 80 100 i s + (2.5v) i s + (5.0v) r l, dm = open circuit 09327-054 figure 24 . ad8146 supply current vs. temperature ?35 ?65 1 1000 freque nc y (mhz) v ocm cmrr (db) 10 100 ?40 ?45 ?50 ?55 ?60 ad814 6 v out, dm / v ocm v ocm = 2v p-p 09327-061 figure 25 . v ocm common - mode rejection ratio 62 48 ?60 120 temperature (c) supply current (ma) 60 58 56 54 52 50 ?40 ?20 0 20 40 60 80 100 r l, dm = open circuit i s + (5.0v) i s + (2.5v) 09327-056 figure 26 . ad8147/ad8148 supply current vs. temperature 1.5 ?1.5 0 40 time (ns) voltage (v) 1.0 0.5 0 ?0.5 ?1.0 5 10 15 20 25 30 35 v s = 2.5v v s = 5.0v v out, cm = 2v p-p 09327-037 figure 27 . ad8146 large signal v ocm transient respons e for various supplies
ad8146/ad8147/ad8148 rev. a | page 14 of 24 theory of operation each differential driver differs from a conventional op amp in that it has two outputs whose voltages move in opposite dire c tions . like an op amp, it relies on high open - loop gain and negative feedback to force these outputs to the desired vol t ages. the drivers make it easy to perform single - ended - to - differential conversion, common - mode level shifting, and a m plification of differential si gna ls. previous differential drivers, both discrete and integrated designs, were based on using two independent amplifiers and two independent feedback loops, one to control each of the outputs. when these circuits are driven from a single - ended source, the resulting outputs are typically not well balanced. achieving a balanced output has typ i cally required exceptional matching of the amplifiers and feedback networks. dc common - mode level shifting has also been difficult with previous differential drivers. l evel shif t ing has required the use of a third amplifier and feedback loop to control the output common - mode level. sometimes, the third amplifier was also used to attempt to correct an inherently unbalanced ci r cuit. excellent performance over a wide freque ncy range has proven difficult with this approach. each of the drivers uses two feedback loops to separately control the differential and common - mode output voltages. the differential feedback, set by the internal resistors, controls only the differentia l output voltage. the internal common - mode feedback loop controls only the common - mode output voltage. this architecture makes it easy to transmit signals over the common - mode voltage channels by simply applying the signal voltage s to the v ocm input s . the output common - mode voltage is forced, by internal common - mode feedback, to equal the voltage applied to the v ocm input, without affecting the differential output vol t age. the driver architecture results in outputs that are highly balanced over a wide freq uency range without requiring external components or adjustments. the common - mode fee d back loop forces the signal component of the output common - mode vol t age to be zeroed. the result is nearly perfectly balanced diffe r ential outputs of identical amplitude that are exactly 180 apart in phase. definition of terms differential voltage differential voltage refers to the difference between two node voltages that are balanced with respect to each other. for exa m ple, in f igure 28 the output differential voltage (or equivalently output diffe r ential mode voltage) is defined as v out, dm = ( v op ? v on ) common - mode voltage common - mode voltage refers to the average of two node voltages with respect to a common refe r ence. the output common - mode vol t age is defined as v out, cm = ( v op + v on )/2 output balance output balance is a measure of how well the differential output signals are matched in amplitude and how close they are to exactly 180 apart in phase. balance is most easily determined by placi ng a well - matched resistor divider between the differe n tial output voltage nodes and comparing the magnit ude of the signal at the dividers midpoint with the magnitude of the di f ferential signal. by this definition, output ba l ance error is the magnitude of the change in output common - mode voltage divided by the magnitude of the change in output differential m ode voltage in response to a diffe r ential input signal. dm out cm out v v error balance output , , ? ? = analyzing an applica tion circuit the drivers use high open - loop gain and negative fee d back to force their differential and common - mode output voltages to minimize the different ial and common - mode input error voltages. the differential input error voltage is defined as the voltage between the differential inputs l a beled v ap and v an in figure 28 . for most purposes, this voltage can be assum ed to be zero. similarly, the difference between the actual output common - mode voltage and the voltage applied to v ocm can also be assumed to be zero. starting from these two assumptions, any applic a tion circuit can be analyzed. closed- loop gain the differential mode gain of the circuit in figure 28 can be de scribed by g f dm in, dm out, r r v v = where: r f is 1.0 k ? and r g is 500 ? nominally for the ad8146 and ad8147 . r f is 2.0 k ? and r g is 500 ? nominally for the ad8148. r g v ap v an v ip v in + v in, dm ? v ocm v on v op v out, dm r g r f r f r l, dm 09327-006 figure 28 . internal architecture and signal name definitions
ad8146/ad8147/ad8148 rev. a | page 15 of 24 calculating the input impedance the effective inp ut impedance of a ci r cuit such as that in figure 28 at v ip and v in depends on whether the amplifier is being driven by a single - ended or diffe r ential signal source. for balanced differential input signals, the diff erential input impe d ance, r in, dm , between the inputs v ip and v in for all devices is r in, dm = 2 r g in the case of a single - ended input signal (for example, if v in is grounded and the input signal is a p plied to v ip ), the input im pedance becomes ( ) ? ? ? ? ? ? ? ? ? ? ? ? + ? = f g f g dm in, rr r r r 2 1 the single - ended input impedance of the ad8146 and the ad8147 is therefore 750 ?, and the single - ended input impedance of the ad8148 is 833 ?. the input impedance of the circuit is effectively higher than it would be for a conventional op amp co n nected as an inverter because a fraction of the differential output voltage appears at the inputs as a common - mode signal, partially bootstrapping the voltage across the input r e sistor r g . input common - mode voltage range i n single - supply application s the driver inputs are designed to faci litate level - shifting of ground - re f erenced input signals on a single power supply. for a single- ended input, this impl ies , for example, that the vol t age at v in in figure 28 wo uld be 0 v when the negative power su p ply voltage of the amplifier i s also set to 0 v. it is important to ensure that the common - mode voltage at the amplifier inputs, v ap and v an , stays within its specified range. because vol t ages v ap and v an are driven to be essentially equal by negative feedback, the input common - mode vol t age of the amplifier can be expressed as a single term, v acm . v acm can be calc u lated as 3 2 icm ocm acm vv v + = where v icm is the common - mode voltage of the input signal, that is , v icm = ( v ip + v in ) /2 . output common - mode control the ad8146 allows the user to control each of the three co m mon - mode output levels independently through the three v ocm input pins. the v ocm pins pass a signal to the common - mode output level of each of their resp ective amplifiers with 330 mhz of small signal bandwidth and an internally fixed gain of 1 . in this way, additional control and communication si gnals can be embedded on the common - mode levels as user s see fit. with no external circuitry, the level at the v ocm input of each amplifier defaults to approximately midsupply. an internal re sistive divider with an impedance of approximately 12.5 k ? sets this level. to limit common - mode noise in dc common - mode applications, external bypass capacitors should be con nected from each of the v ocm in put pins to ground. sync - on common - mode the ad8147 and ad8148 are specifically targeted at driving rgb video si g nals over utp cable using a sync - on common - mode technique . the common - mode outputs of each of the r, g, and b dif ferential ou t puts are set using circui try contained within the device. this circuitry embeds the hor i zontal and vertical sync pulses on the three common - mode outputs in a way that also results in low rad i ated energy. for a more detailed description of the sync scheme, see the applications se c tion. the sync - on common - mode circuit generates a current based on the sync level input pin (pin 18). with the sync level input tied to gnd, the common - mode output of all driver s is set at (v s+ + v s? )/2. using a resistor divider, a voltage can be applied between gnd and sync level that dete r mines the max i mum deviation of the common - mode outputs from their midsupply level. if, for instance, sync level = 0.5 v and the supply voltage is 5 v, the co m mon - mode outputs fall within an envelope of 2.5 v 0.5 v. the state of each v o u t, c m output based on the h sync and v sync inputs is dete r mined by the equations defined in the applications section. in most cases , t he s ync - on common - mode circuit can be used by directly applying the h sync and v sync signals to the ir re spective ad8147 or ad8148 inputs. the logic thresholds of the h sync and v sync in puts are set to nominally 1.4 v with respect to gnd, and the exposed paddles of the ad8147 and ad8148 are used as the gnd references for the incoming sync pulses . when 2.5 v supplies are used, however, external protection is required to limit the p ositive excursion to less than 2.5 v. for more detail s, see the applications section. the input path s from the h sync and v sync in puts to the switches in the current mode level - shifting circuit are well matched to eliminate false switc h ing transients, maximizing common - mode balance and minimizing rad i ated energy.
ad8146/ad8147/ad8148 rev. a | page 16 of 24 applications driving rgb video si gnals over cat e gory - 5 utp cable the foremost application of the drivers is the transmission of rgb video si g nals over utp cable in kvm networks. the excellent balance of the differential outputs e n sure s low radiated energy from each of the twisted pairs. single - ended video signals are easily converted to differential signals for transmi s sion over the cable, and the internally fixed gain of 2 or 4 automatically co m pensates for the losses incurred by the source and load termin a tions. the common topologies used in kvm networks, such as daisy - chained, star, and point - to - point, are su p ported by the drivers. figure 29 shows the ad8146 in a triple single - ended - to - differ ential applic a tion when driven from a 75 ? source, which is typical of how rgb video is driven over an utp cable. v ocm +2.5v ? out a + a 1k? video source a 1k? ad8146 500? 82.5 ? 39.2 ? 39.2 ? 39.2 ? 500? 49.9 ? 49.9 ? 75? v ocm +2.5v ? out b + b 1k? video source b 1k? 500? 82.5 ? output pulldown 500? 49.9 ? 49.9 ? 75? v ocm +2.5v ? out c + c 1k? video source c 1k? 500? 82.5 ? 500? opd 49.9 ? 49.9 ? 75? +5v v s+ 0.1f on all v s+ pins v s? 09327-007 figure 29 . ad8146 in single - ended -to- differential application video sync -on common -mode in computer video applications, the hori zontal and vertical sync signals are often separate from the video information si gnals. for example, in typical computer monitor applications, the red, green, and blue (rgb) color signals are transmitted over separate cables, as are the vertical and horizontal sync si g nals. when transmitting these types of video signals over long distances on utp cable, it is desirable to reduce the required number of physical channels. one way to do this is to encode the vertical and horizontal sync signals as weighted sum s and differences of the output common - mode signals. the rgb color signals are each transmitted differentially over separate physical channels. the fact that the differential and common - mode si g nals are orthogonal allows the rgb color and sync signals to b e separated at the channels receiver. cat - 5 cable contains four balanced twisted - pair physical channels that can support both differential and common - mode sig nals. transmitting typical computer monitor video over this cable can be a c complished by using three of the twisted pairs for the rgb and sync signals and one wire of the fourth pair as a return path for the schottky diode bias currents. each color is transmitted differe n tially, one on each of the three pairs, and the encoded sync signals are transmi tted among the co m mon - mode signals of each of the three pairs. to minimize emi from the sync signals, the common - mode signals on each of the three pairs produced by the sync encoding scheme induce electric and magnetic fields that for the most part cancel each other. a conceptual block diagram of the sync encoding scheme is pr e sented in figure 30. because the ad8147 / ad8148 have the sync encoding scheme implemented internally, the user simply applies the horizontal an d vertical sync signals to the appropriate in puts. (see the specifications t ables for the high and low levels of the horizontal and vertical sync pulse vol t ages).
ad8146/ad8147/ad8148 rev. a | page 17 of 24 ?out r +out r ?out g +out g ?out b +out b v ocm weighting equations: red v ocm = k (v sync ? h sync ) + v midsupply green v ocm = k (?2v sync ) + v midsupply blue v ocm = k (v sync + h sync ) + v midsupply +in r ?in r v sync h sync sync level +in g ?in g +in b ?in b r 1k? 1k? ad8147/ad8148 500? 500? g 1k? 1k? 500? 500? v ocm v ocm v ocm b 1k? 1k ? 500? 500? opd 2 2 2 2 09327-008 figure 30 . ad8147/ad8148 sync - on common - mode encoding scheme 0 0.5 1.0 1.5 2.0 4.0 3.5 4.5 2.5 3.0 5.0 0.98 0.99 1.00 1.01 1.03 1.04 1.05 1.02 1.06 1.07 time (s) h sync v sync 2.0 2.1 2.2 2.3 2.4 2.9 2.8 3.0 2.5 2.6 2.7 3.1 r g b volts volts 09327-009 figure 31 . ad8147 sync - on common- mode signals in single 5 v application the transmitted common - mode sync signal magnitudes are scaled by applying a dc voltage to the sync level input, referen ced to gnd. the difference between the voltage a p plied to the sync level input and gnd sets the peak deviation of the encoded sync signals about the midsupply , common - mode vol t age. for example, with the sync level input set at 500 m v, t he deviation of the encoded sync pulses about the nominal midsupply , common - mode voltage is typ i cally 500 m v. t h e equations in figure 30 describe how the v sync and h sync signals are encoded on each colors midsu p ply common - mode signal . in these equations, the weights of the v sync and h sync signals are 1 (+1 for high and ?1 for low), and the constant k is equal to the peak deviation of the encoded sync signals. figure 31 shows how the sync signals appear on each common - mode voltage in a single 5 v supply application when the vol t age applied to the sync level input is 500 mv, which is the typical setting for most applications.
ad8146/ad8147/ad8148 rev. a | page 18 of 24 sync pulse amplitudes applied to the ad8147 and ad8148 mus t be less than or equal to the positive supply voltage. i n low positive supply applications , such as those that use 2.5 v supplies , external limiting may be required because m any logic families produce amplit udes up to 5 v. figure 32 illustrates how to use a mono lithic triple diode to limit a sync pulse with 5 v amplitude to an amplitude of approximately 2 v. 301? 1 6 2 5 3 4 hn2d02futw1t1 0v +5v incoming sync pulse 0v +2v limited sync pulse 06655-036 figure 32 . limiting sync pulse amplitude in low positive supply applications driving two utp cabl es w i th one driver some applications require driving two utp cables with a single driver. each individual driver of the ad8146 / ad8147 / ad8148 is capable of driving two doubly terminated cables, which places a differential load of 100 ? across the output s of the driver. figure 33 illustrates how to drive two cables. ad8146/ad8147/ad8148 49.9 ? 49.9 ? 100? 100? 100? utp 49.9 ? 49.9 ? 100? utp v ocm 09327-034 figure 33 . driving two utp cables with one driver driver bandwidth is affected to a small degree when driving the 100 ? load presented by the two cables , as compared with driving a typical 200 ? load . figure 34 illustrates the ad8146 / ad8147 / ad8148 bandwidths when driving a 100 ? lo ad. 15 ?3 frequency (mhz) gain (db) 12 9 6 3 0 1000 100 10 1 ad8148 ad8147 ad8146 r l, dm = 100 ? v out = 2v p-p 09327-044 figure 34 . large signal frequency response driving 100 ? loads using the ad8146 as a receiver while the ad8146 excel s as a differential driver, it can also be used as a d ifferential - to - differential receiver applied as an inp ut buffer that protects a more sophisticated device, such as a differential crosspoint switch. see figure 35 for an illustration of this type of application. becaus e the ad8146 v ocm input pins are uncommitted, any incoming common - mode signal , such as encoded sync pulses, can be reproduced at the ad8146 outputs by stripping it from the received signal and applying it directly to the v ocm pin. the two series 54 .9 ? resistors form a differential termination resistor of 109.8 ?, which when loaded with the 1 k ? differential inp ut resistance of the ad8146, provides an overall termination of approximately 100 ?. the received common - mode volta ges are available at the center tap s between the two resistors.
ad8146/ad8147/ad8148 rev. a | page 19 of 24 ad8146 crosspoint switch 54.9 ? 54.9 ? 1k? 1k? 500? 500? input i, negative phase input i, positive phase input j, negative phase input j, positive phase input k, negative phase input k, positive phase 10? 10? v ocm red channel 100? utp 54.9 ? 54.9 ? 1k? 1k? 500? 500? 10? 10? v ocm green channel 100? utp 54.9 ? 54.9 ? 1k? 1k? 500? 500? 10? 10? v ocm blue channel 100? utp v s+ = +2.5v vpos = +2.5v vneg = ?2.5v v s? = ?2.5v 09327-035 figure 35 . using the ad8146 as a differential receiver terminations are not required between the ad8146 and the switch if the interconnection lengths are kept short (less than two inche s). the 10 ? series resistors buffer the input capacitance of the switch (typically 2 pf) and produce a low - pass rolloff that is down by only 0.025 db at 600 mhz. output pull - down (opd) the output pull - down feature, when used in conjunction with series schottky diode s, offers a conve n ient means to multiplex a number of driver outputs together to form a video ne t work. the opd pin is a binary input that controls the state of the ou tputs. its binary input level is refe r enced to gnd (see the specifications section for the logic levels). when the opd input is driven to its low state, the output is enabled and operates in no r mal fashion. in this state, the v ocm input can be used to provide a positive bias on the series diodes, a l lowin g the drivers to transmit signals over the ne t work. when the opd input is driven to its high state, the ou t puts of the drivers are forced to a low voltage, irrespective of the level on the v ocm input, reverse - biasing the se ries diodes and thus presenting h igh impedance to the network. this feature allows a three - state output to be rea l ized that mai n tains its high impedance state even when the drivers are not powered. it is recommended that the output pull - down feature only be used in conjunction with serie s diodes in such a way as to ensure that the diodes are reverse - biased when the output pull - down fe a ture is asserted, because some loading conditions can prevent the ou t put voltage from being pulled all the way down. layout and power sup ply decou p ling considerations standard high speed pcb layout practices should be adhered to when designing with the drivers. a solid ground plane is required and good wideband power supply decoupling ne t works should be placed as close as possible to the supply pins. s ma ll surface - mount ceramic capacitors are reco m mended for these networks, and tantalum capacitors are re c ommended for bulk supply decoupling. source termination resistors on the differential outputs must be placed as close as possible to the output pins to m inimize load capacitance due to the pcb traces. driving a capacitive load a purely capacitive load can react with the output impedance of any amplifier to produce an undesirable phase shift, which reduces phase margin and results in high fr e quency ringing in the pulse response. the best way to minimize this effect is to place a small resistor in series with each of the outputs of the amplifier to buffer the load capacitance. most applications include 49.9 ? source termination resistors, which effectively b uffer any stray load capacitance.
ad8146/ad8147/ad8148 rev. a | page 20 of 24 under no circumstances should capacitance be intentionally added to an output to introduce frequency domain peaking. figure 36 and figure 37 illustrate how adding just 5 pf of excessive load capacitance influences time and frequency domain responses. 2.0 ?2.0 0 20 time (ns) voltage (v) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 2 4 6 8 10 12 14 16 18 v s = 5v r l, dm = 200 v out, dm = 2v p-p c l = 5pf c l = 0pf 09327-031 figure 36 . large signal transient responses at various capacitive loads 12 2 10 1000 frequency (mhz) gain (db) 100 11 10 9 8 7 6 5 4 3 v s = 5v r l, dm = 200 v out, dm = 2v p-p c l = 5pf c l = 0pf 09327-032 figure 37 . large signal frequency responses at various capacitive loads while high frequency peaking is desirable in some cable equalization applications, it should be implemented using methods that do not compromise the stability of the driver and that do not depend on a mplifier parasitic elements. the parasitic elements are affected by process variations and cannot be depended upon for circuit designs. the amplifier may break into oscillation when excess load capacitance is intentionally added. for more information on th is topic, s ee the adding pre - emphasis to the ad8148 section for a description on how to introduce a controlled amount of pre - emphasis for 30 meters of utp using the ad8148. adding pre - emphasis to the ad81 48 u tp cables exhibit loss characteristics that are low pass in nature and are exponential functions of the square r oot of the frequency. over wideband video bandwidths , t he losses are predominant ly due to the skin effect, which causes the resistance of the ca ble to increase with frequency. even though the loss characteristics are nonlinear, suitable linear networks can be designed to approximately compensate for the losses. placing the compensation network at the transmitting end of the cable is referred to as pre - emphasis, becaus e the higher frequencies are emphasized, or boosted, before they are sent , to compensate for the low - pass response of the cable . because t he higher frequencies experience more loss than the lower frequencies as they pass through the ca ble, the high and low frequencies arrive at approximately the same level and at the end of the cable when a properly designed pre - emphasis network is used at the transmitter . t he ideal cascaded frequency response of the pre - emphasis network and the cable i s therefore nominally flat. because the ad8148 has an internally set , closed - loop gain of 4 (12 db) , it is possible to reduce the gain at low frequencies using external frequency selective components , then use these components to provide increasing gain wi th increasing frequency , back to a value close to 12 db . these components, along with the ad8148 , form the pre - emphasis network. when properly des igned, the combined frequency response of the pre - emphasis network and cable is approximately flat with a gai n of 2 (6 db) . figure 38 illustrates how to construct a pre - emphasis network using the ad8148 that compe nsates for 30 meters of utp cable. the network in the lower leg is required to match the transfer function of the two feedback loops. at dc , th e capacitors are open circuits , and the network has a gain of approximately 6.5 db. (the additional 0.5 db is added to compensate for the cable flat loss that occurs at frequencies below where the skin effect begins to take effect.) moving up in frequency, the 30 pf capacitor begins to take effect and introduces a zero into the frequency response, causing the gain to increase with frequency. continuing to move up in frequency, the 30 pf capacitor becomes an effective short, and the 487 ? resistor goes in parallel with the 442 ? resistor, forming a pole in the response. continuing to move up in frequency, the 1 8 pf capacitor takes effect, introducing another zero, and causes the gain to further increase with frequency until i t becomes an effective short , and the gain starts to fla tten out until the amplifier response begins to roll off. the gain does not reach 12 db before the amplifier begins to roll off because the 12 db value is a high frequency asymptote. the pole and zer o locations cited in the previous discussion are qualitative , but the discussion describes the basic principles involved with the operation of the pre - emphasis network.
ad8146/ad8147/ad8148 rev. a | page 21 of 24 figure 39 illustrates the frequency response of the pre - emphasis network. figure 40 illustrates the frequency response of the pre - emphasis circuit cascaded with the cable compared with that of the cable alone. it can be seen that the overall response is fla t to within 0.4 db. the 0.4 db ripple in the response is due to the fact that the pre - emphasis network is linear, comprised of two real - axis pole/zero pairs, and the cable response is nonlinear. exposed paddle (ep) the 24 - lead lfcsp has an exposed paddle on the underside of its body. to achieve the specified thermal resi s tance, it must have a good thermal connection to one of the pcb planes. the exposed paddle must therefore be soldered to a pad on the top of the board that is connected to an inner plane with several the r mal vias. the ad8147/ad8148 use the paddle as a ground reference; therefore, for these parts, the pcb plane used must be the ground plane. 2k? 2k? 500? 500? 49.9 ? 49.9 ? 442? 82.5 ? 487? 39.2 ? 442? 487? 75? 100 feet 100? utp ad8148 + ? video source 18pf 30pf 18pf 30pf 09327-048 figure 38 . pre - emphasis network using the ad8148 for 30 m eters of utp c a ble 12 6 frequency (mhz) gain (db) 11 10 9 8 7 100 10 1 0.1 v s = 5v 09327-049 figure 39 . ad8148 pre - emphasis network frequency response 9 ?9 0.1 frequency (mhz) gain (db) 6 3 0 ?3 ?6 1 10 100 pre-emphasis network with cable cable alone v s = 5v 09327-050 figure 40 . ad8148 pre - emphasis network cascaded with 30 meters of utp cable vs. utp cable alone
ad8146/ad8147/ad8148 rev. a | page 22 of 24 outline dimensions 1 24 6 7 13 19 18 12 2.25 2.10 sq 1.95 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indica to r top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vggd-2 072208-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 41 . 24 - lead lead frame chip scale package [lfcsp _vq ] 4 mm 4 mm (cp - 24 -1) dimensions shown in millimeters ordering guide model 1 temperature range package description package o ption ad8146acpz -r2 ?40c to +85c 24- lead lead frame chip scale package [lfcsp _vq ] cp -24 -1 ad8146acpz -r7 ?40c to +85c 24- lead lead frame chip scale package [lfcsp _vq ] cp -24 -1 ad8146acpz -rl ?40c to +85c 24- lead lead frame chip scale package [lfcsp _vq ] cp -24 -1 ad8147acp z-r2 ?40c to +85c 24- lead lead frame chip scale package [lfcsp _vq ] cp -24 -1 ad8147acpz -r7 ?40c to +85c 24- lead lead frame chip scale package [lfcsp _vq ] cp -24 -1 ad8147acpz -rl ?40c to +85c 24- lead lead frame chip scale package [lfcsp _vq ] cp -24 -1 ad81 48acpz -r2 ?40c to +85c 24- lead lead frame chip scale package [lfcsp _vq ] cp -24 -1 ad8148acpz -r7 ?40c to +85c 24- lead lead frame chip scale package [lfcsp _vq ] cp -24 -1 ad8148acpz -rl ?40c to +85c 24- lead lead frame chip scale package [lfcsp _vq ] cp -24 -1 1 z = rohs compliant part.
ad8146/ad8147/ad8148 rev. a | page 23 of 24 notes
ad8146/ad8147/ad8148 rev. a | page 24 of 24 notes ? 2007 - 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09327 -0- 8/10(a)

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